Program
Day 1 (July 31st)
from 9:30
Registration and welcome coffee10:00 – 10:25
Welcome to Heidelberg and FPGA Ignite 202310:30 – 12:30
Lightning talks12:30 – 13:45
Lunch (Bräustüble)13:45 – 15:00
Keynote LegUp High-Level Synthesis and its Commercialization Prof. Jason Anderson, University of Toronto, CA15:00 – 16:00
Attendee Poster Session (click here for more details)16:00
Hike to Neuburg Abbey (over the Philosophers’ Walk) and dinner (18:00) at Klostergarten
Day 2 (August 1st)
High-Level-Synthesis (Jason Anderson) click here for the materials
8:45
Registration9:00 – 12:30
Morning classes (Coffee break at 10:30)- What is HLS (and what are its limitations)
- How does it work
- How to use HLS
12:30 – 13:45
Lunch (Rosetto)13:45 – 17:00
Afternoon labs (Coffee break at 15:15)18:00
Dinner (Marstall Mensa)19:30-21:00
Guided City Tour (Start: Universitätsplatz)
Day 3 (August 2nd)
Logic Synthesis with Yosys (Nina Engelhardt, YosysHQ) Presentation / Lab materials / Solution
8:45
Registration9:00 – 12:30
Morning classes- Basics of Logic Synthesis
- Yosys for scientific research
(data formats, circuit transformations, custom plugins)
12:30 – 13:45
Lunch (Mensa)13:45 – 17:00
Afternoon labs (Coffee break at 15:15)19:00
Evening Event (Kulturbrauerei Heidelberg)
Day 4 (August 3rd)
8:45
Registration9:00 – 10:30
Morning classes (Coffee break at 10:30)11:00 – 12:30
Morning classes- Bitstream generation for FABulous FPGAs
- nextpnr (Rowan Goemans) Slides
12:30 – 13:45
Lunch (Bräustüble)13:45 – 15:15
Open-source ASIC design (Nguyen Dao [eFPGA_Slides], Gavaskar)- OpenLane tool (Verilog to GDS2)
- KLayout
15:15 – 15:45
Coffee break15:45 – 17:00
Labs
Day 5 (August 4th)
Hackathon
9:00 – 10:30
From Zero to ASIC in a nutshell (Matt Venn)from 10:30
Happy FPGA Hacking- (design a custom FPGA Tile; supported by Nguyen, Myrtle, and Gavaskar)
- OpenLane_Tutorial: Hardening the core
- OpenLane_Tutorial: Hardening Macros
- Open Source Asic Design
16:30
Pizza and Best Design Award
Presentations
| Presenter | Bio | Title | Abstract | Co-authors | |
|---|---|---|---|---|---|
| Hassan Nassar | Hassan Nassar received the B.Sc. degree (Highest Hons.) from German University in Cairo, New Cairo City, Egypt, in 2016, and the M.Sc. degree from Ulm University, Ulm, Germany, in 2019. He joined the Chair for Embedded Systems in March 2020 as a Research Assistant. His research interests are hardware security, reconfigurable architectures, memory reliability, and cloud FPGAs. I consent to adding the information to the website Slides are attached. | LoopBreaker: Disabling Interconnects to Mitigate Voltage-Based Attacks in Multi-Tenant FPGAs | LoopBreaker is a a novel runtime solution designed to mitigate FPGA fault attacks in cloud environments. These attacks can be launched by malicious tenants to cause timing faults or crashes in other regions. Unlike existing offline countermeasures that have limitations and may reveal design secrets, LoopBreaker operates online and can disable the entire activity of a malicious tenant region within a rapid timeframe of 1.5 µs, preventing potential Denial-of-Service (DoS) crashes effectively. | Hanna Alzughbi, Dennis Gnad, Lars Bauer, Mehdi Tahoori, Joerg Henkel | |
| Dominik Walter | Dominik Walter received his M.Sc. degree in computer science from University of Augsburg, Germany, in 2019. Since then, he is researching massively parallel processor architectures at the chair for Hardware/Software Co-design (FAU). | ALPACA: Asic LooP ACcelerAtor | The ASIC Loop Accelerator - ALPACA for short - is a fully fledged ASIC in 22~nm FDSOI technology. It consists of 64 processing elements, each capable of processing 3 32-bit floating point vector instructions simultaneously. The chip contains 6 million standard cells on a chip area of 10 square millimetres and was manufactured by Global Foundries in Dresden, Germany. | Marcel Brand, Christian Heidorn, Dominik Walter, Michael Witterauf, Frank Hannig, Jürgen Teich | Onsite |
| Werner Florian Samayoa | Werner Florian Samayoa received the B.S. degree in electronics engineering from the University of San Carlos, Guatemala, in 2018. He is currently pursuing the Ph.D. degree in industrial and information engineering with the Multidisciplinary Laboratory (MLab), The Abdus Salam International Center for Theoretical Physics, Universitã degli Studi di Trieste, under the Joint-Supervision Program. His research interest includes scalable reconfigurable supercomputing. | HyperFPGA experimental reconfigurable supercomputing platform | The HyperFPGA is a scalable SoC-FPGA-based cluster aimed at exploring reconfigurable high-performance computing. HyperFPGA offers a flexible and programmable infrastructure that combines field-programmable gate arrays (FPGAs) with CPUs and high-speed general-purpose connectors. The flexibility of the platform extends to communication protocols at the hardware level, ideal for experimenting with novel architectures and interconnects. A Linux OS and custom driver, along with a Message Passing Interface (MPI), offer a programmable framework for firmware and task deployment. Overall, the testing of HyperFPGA using the N-Queens problem highlights the platform's ability to handle computationally intensive tasks and suggests its suitability for use in supercomputing. | Maria Liz Crespo, Sergio Carrato, Agustin Silva, Andres Cicuttin | Onsite |
| Marko Andjelkovic | Dr.-Ing. Marko Andjelkovic received Dipl-Ing. degree in Electronics from the Faculty of Electronic Engineering, University of Nis (Serbia), in 2008. In 2021, he has received Dr.-Ing. degree in the field of fault tolerance in computing architectures, from the University of Potsdam (Germany). Since 2016 he is with IHP, where he is employed as a scientific researcher at the System Architectures department. His research is related to the characterization and modeling of fault effects in CMOS digital circuits, on-chip fault sensing, and design of fault-tolerant circuits and systems. | Towards a Rad-Hard Baseband Processor for 6G Non-Terrestrial Networks | The next generation of mobile communication systems, i.e., 6G communication networks, aim to achieve global, secure, reliable and intelligent connectivity by integrating terrestrial networks with airborne networks (drones, helicopters, etc.) and spaceborne networks (orbital satellites). To achieve this goal, new technologies and components are required. In this work, we present the initial design concept of a radiation-hardened baseband processor for satellite communications within 6G networks. | Nebojsa Maletic, Milos Krstic | |
| Junchao Chen | Junchao Chen received the Dr.-Ing degree from the Potsdam University, Germany, in 2023, on the topic of ”A Self-adaptive Resilient Method for Implementing and Managing High-reliability Processing Systems.” Since 2018, he has been a member of Prof. Milos Krstic’s ”Fault-tolerance Computing” research group at IHP Microelectronics in Frankfurt (Oder), Germany. His research interests include self-adaptive fault-tolerance mechanisms, radiation-induced effects, high-reliability system design, and agile hardware development. Throughout his academic career, he has participated in several international and national research projects. He has published over 20 journal and conference papers and has been granted one patent. | The TETRISC SoC - A Robust Quad-Core High Resilience System | ault-tolerant systems are typically designed for worst-case scenarios and offer sub-optimal performance during normal operation. Configurable systems that adapt to changing circumstances can improve this situation. This poster presents a design of TETRISC SoC, which is a multiprocessor system based on the Pulpissimo platform that uses various reliability sensors to operate its four cores in different performance and fault tolerance modes as needed. This adaptable solution provides optimal performance and reliability for use cases with high requirements, such as avionics or aerospace. | Rizwan Tariq Syed, Marko Andjelkovic, Lara Wimmer, Eckhard Grass, Markus Ulbricht, and Milos Krstic | |
| Anis Hamadouche | Anis Hamadouche is a final-year PhD student from Heriot-Watt University. Mr. Hamadouche’s work consists of theoretically analyzing the performance of iterative optimization algorithms, such as proximal algorithms and alternating direction method of multipliers (ADMM), when the internal operations of the algorithms are executed with errors. The types of errors considered stem from approximations at hardware and software levels, for example, quantization under different types of numerical representations, including fixed- and floating-point representations. Although this work is very theoretical, it has wide-ranging implications. In fact, in contrast with prior work, it considers realistic error models and implementation in platforms like FPGAs. Mr. Hamadouche’s PhD is associated with the UDRC Phase III programme (https://udrc.eng.ed.ac.uk/), sponsored by UKRI’s EPSRC and the MoD. And, in this context, he has explored applications in control and image processing. | Design and Implementation of Approximate Operator Splitting Algorithms On FPGA | Any algorithm requires a computational platform to run. Some platforms, however, have limited size, power, or energy, especially if they are battery-operated. Examples include cell phones, unmanned vehicles like flying drones, or tiny sensors. Yet, they need to process information to make inferences about a signal or to compute a trajectory, which is done by running algorithms that often require a considerable amount of computation. Our goal is to investigate ways to reduce the total amount of power/energy/size of an algorithm by considering the full computational stack: from the task itself, to its algorithmic implementation, basic linear algebra operations, software, and hardware. Indeed, in each of these layers, there exist techniques to reduce power/energy/size, for instance, by reducing voltage or frequency, selecting a lower precision for representing numbers, or using approximate algorithms in linear algebra operations. However, such techniques are almost always considered in isolation without taking into account the impact on the downstream task. In this WP, we took a holistic view on this set of approximations and developed strategies to select the most effective approximations without undermining the task at hand. We thus made several experimental and theoretical contributions to the field. | Yun Wu, Andrew M. Wallace, and Joao F. C. Mota | |
| Anthony Etim | Anthony Etim is a second year Ph.D. student at Computer Architecture and Security Lab, Yale University. His research interests lie in Computer architecture and Security, especially focusing on cloud infrastructures and the security of FPGA-accelerated cloud environments by evaluating and defending various types of side channels and covert channels, as well as how to enable secure multi-tenant Cloud FPGAs. | Thermal Covert Channels on smartSSDs | Continued expansion of cloud computing offerings now includes SmartSSDs. Because of the FPGA component of the SmartSSD, cloud users who access the SmartSSD can instantiate custom circuits within the FPGA. This includes possibly malicious circuits for measurement of power and temperature. Normally, cloud users have no remote access to power and temperature data, but with SmartSSDs they could abuse the FPGA component to learn this information. This work shows for the first time that heat generated by a cloud user accessing the SSD component of the SmartSSD and the resulting temperature increase, can be measured by a different cloud user accessing the FPGA component of the same SmartSSD by using the ring oscillator (RO) circuits to measure temperature. The thermal state remains elevated for a few minutes after the SSD is heated up and can be measured from the FPGA side by a subsequent user for up to a few minutes after the SSD heating is done. Based on this temporal thermal state of the SmartSSD, a novel thermal communication channel is demonstrated for the first time. | Theodoros Trochatos and Jakub Szefer | |
| Ingo Hoyer | Ingo Hoyer has received a bachelors and masters degree in electrical engineering from the Technical University of Darmstadt, Germany. Since June 2022 he is PhD student at Fraunhofer IMS in Duisburg, Germany. His research interests are AI accelerators, RISC-V and reconfigurable hardware. | In recent years, RISC-V-based SoC implementations for local signal processing has become a focus of the department for Smart Sensor Systems at Fraunhofer IMS. Challenges of adaptability, power constraints and performance requirements have been addressed using instruction set extensions such as single instruction multiple data operations as well as designated peripheral neural network accelerators. Implementing flexible fabrics into the SoC solutions brings new opportunities for the applications in various domains, e. g. biosignal analysis, industrial condition monitoring or smart farming. | Alexander Utz, Holger Kappert and Karsten Seidl | Onsite | |
| Robin Heinemann | Robin Heinemann is a masters student at the university of Heidelberg. Since 2018 he is part of the apertus open source cinema project, developing software, hardware and HDL for open source cinema cameras. Jaro Habiger is a student at the University of Applied Arts Vienna. Since 2017 he is part of the apertus project developing open source cinema cameras. He has been part of art-projects involving FPGAs and video processing. | naps | The `naps` package is a collection of video focused IP-cores combined with advanced code generation for SoC use cases. Using Amaranth HDL, it facilitates rapid co-development by enabling HDL and software to be written in the same language and comined in the same python class hierarchy. Python software code can transparently access control and status registers (CSRs) allowing even interactive exploration of the combined HDL and software system. | Jaro Habiger | |
| Sara Hoseininasab | Sara Hoseininasab is currently working toward a Ph.D. degree in computer science at the University of Rennes, Rennes, France, under the supervision of Steven Derrien and Caroline Collange. She received an M.Sc. degree from the University of Isfahan, Isfahan, Iran. Her research interests include computer architecture, hardware design, and high-level synthesis. Contact her at sara-sadat.hoseininasab@inria.fr. | Rapid Prototyping of Complex Micro-architectures through High-Level Synthesis | In this work, we show how to exploit HLS features to synthesize complex micro-architectures without delving into RTL implementation. We take advantage of multi-threading and dynamic scheduling to synthesis various classes of micro-architectures by HLS from an Instruction Set Simulator(ISS) written in C. | Caroline Collange, Steven Derrien | |
| Andreas Erbslöh | Andreas Erbslöh received the master’s degree in electrical engineering and the Dr.-Ing. degree from the University of Duisburg-Essen, Germany, in 2015 and 2021, respectively. Currently, he is working as a scientific researcher with the Department of Embedded Systems. His research interests include methods and corresponding CMOS circuit design for the simultaneous electrical stimulation and recording of neural activities, including hardware friendly integration of low-power neural signal processing (e.g. spike sorting) and neural decoders for future neural devices. | This paper presents the elasticAI workflow for creating and deploying deep learning accelerators for embedded systems. This workflow considers the model training with hardware templates with PyTorch, the Synthesis of the model in Vivado and the hardware run on the FPGA. These accelerators can be used as neural signal processor in future neural devices like retinal implants and brain computer interfaces in order to restore sensory loss due to neurogenerative diseases. | Chao Qian, Lukas Einhaus, Leo Buron, Andreas Erbslöh, Gregor Schiele |
Main Sponsor
Further support is proved through the UK EPSRC programme grant FORTE (grant agreement EP/R024642/1)
Registration
Thanks to support from Carl-Zeiss-Stiftung, FPGA Ignite 2023 is free of charge to attend.
(Attendees will have to arrange/pay travel and accommodation on their own. The Central Hotel and the Ibis are in walking distance to the main train station and the venue and usually reasonably priced)
All FPGA Ignite 2023 places have been taken, and we cannot accept any further application.
Thanks for your understanding!
Venue
The first day, the classes and the Hackathon will take place at the Käthe Leichter Forum (Graduiertenakademie) Address: Im Neuenheimer Feld 370, 69120 Heidelberg
